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| Title: |
TEM of silicon nanowire |
| Description: |
In this transmission electron micrograph, a silicon nanowire is shown surrounded by a stack of thin layers of material called dielectrics, which store electrical charge. NIST scientists determined the best arrangement for this dielectric stack for the optimal construction of silicon nanowire-based memory devices. Color added to image.
See also http://www.nist.gov/pml/semiconductor/nanowire-052411.cfm.
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| Subjects (names): |
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| Topics/Categories: |
Nanotechnology--Materials
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| Type: |
Photo/Color |
| Source: |
National Institute of Standards and Technology |
Credit Line as it should
appear in print: |
Bonevich/NIST |
| AV Number: |
11PML049 |
| Date Created: |
2011 |
| Date Entered: |
5/18/2011 |
